In silicon semiconductor integrated circuit fabrication, it is important to be able to test the circuit structures to ensure design specifications are met and to isolate sources of defects in the wafer processing. In general, it has heretofore been impractical to test each layer or fabrication step while the step is in production. Only limited in-process testing has been possible because of the time and expense involved. The available in-process testing methods only give limited information which is both untimely and inadequate. For example, these testing methods do not provide information about the level of fabrication on which any failure occurred or what the failure percentage is (defect density). Circuit testing structures pre-formed on the circuit after complete fabrication give even more limited information on processing and design errors.
One prior method of testing comprises the placing of a test structure comprising a comb structure with interleaving tines and integral probe pads on the semiconductor wafer. The test structure is built during the integrated circuit fabrication or on a separate pilot wafer and reflects the structures and intricacy required therein. Once the integrated circuit is completed, a mechanical probe testing device is used to contact the probe pads on the test structure and an electrical readout is obtained. The readout provides little more than a pass/fail indication with no fault location information.
Additionally, the use of a mechanical probe testing device requires the use of probe pads for contact between the test structure and the probes. Since the probe pads often require significantly more space than the test structure itself, due to the size of the probes, there is an inherent wasting of valuable wafer surface space. Thus there is a need for a method and apparatus that will allow the identification of fault location, fault density and fault type and is space efficient.